Interrupt signals’ register.
| RECEIVE_INT_ST | 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset |
| TRANSMIT_INT_ST | 1: this bit is set whenever the transmit buffer status changes from ‘0-to-1’ (released) and the TIE bit is set within the interrupt enable register. 0: reset |
| ERR_WARNING_INT_ST | 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset |
| DATA_OVERRUN_INT_ST | 1: this bit is set on a ‘0-to-1’ transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset |
| TS_COUNTER_OVFL_INT_ST | 1: this bit is set then the timestamp counter reaches the maximum value and overflow. |
| ERR_PASSIVE_INT_ST | 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset |
| ARBITRATION_LOST_INT_ST | 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset |
| BUS_ERR_INT_ST | 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset |
| IDLE_INT_ST | 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset |